With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor memory devices that operate at higher speeds and lower power and that have increased device density. To accomplish this, devices with aggressive scaling and multiple-layered devices with transistor cells arranged in horizontal and vertical arrays have been under development.
In contemporary non-volatile memory devices, programming operations are performed by applying a programming voltage Vpgm to a word line of a memory cell to be programmed, while a pass voltage Vpass is applied to word lines of unselected cell strings. At the same time, a ground voltage 0V is applied to a bit line of the cell string including the memory cell to be programmed, while a power voltage Vcc is applied to the bit lines corresponding to cell strings of unselected memory cells.
The programming voltage Vpgm is generally a very high voltage, such as 20V, which is strong enough to cause injection of electrons into the charge storage layer of the memory cell to be programmed. The electron injection is a result of the electric field generated between the control gate of the memory cell to be programmed to which the programming voltage Vpgm is applied, and the channel region of the memory cell to be programmed to which the ground voltage 0V is applied via the bit line. The resulting injection of electrons into the charge storage layer of the desired memory cell operates to program the memory cell.
Application of the programming voltage Vpgm to the word line connected to the memory cell to be programmed can also lead to inadvertent programming of other memory cells in other cell strings connected to the same word line. For this reason, a self-boosting programming operation has been developed by which the power voltage Vcc, rather than the ground voltage, is applied to the bit lines corresponding to cell strings of unselected memory cells. The self-boosting programming operation boosts the potential in the channel regions of transistors of the unselected cell strings, thereby reducing the electric field in the memory cells sharing the same word line as the selected memory cell. The reduced electric field is insufficient for causing the programming of cells in the unselected cell strings.
The self-boosting programming operation described above can modify the threshold voltages of other memory cells of the selected cell string and can modify the threshold voltages of other memory cells of unselected cell strings connected to the selected word line. Modification of the threshold voltages can cause overlapping of the program and erase voltages of the affected cells, which can lead to device malfunction. As devices become more highly integrated, lowering of the programming voltage Vpgm and the pass voltage Vpass is desired, rendering the resulting device more susceptible to the threshold voltage overlapping problem.
Further, as devices continue to become more highly integrated, unwanted programming of memory cells driven by the word line closest in proximity to the ground select line (GSL) can occur. Such programming occurs due to an effect known as Gate Induced Drain Leakage (GIDL). The GIDL effect results in the formation of an electron-hole pair. In one example, an electron-hole pair can be created when an electric field greater than about 1 MV/cm is applied. With further integration of devices, the electric field concentration is generally increased, which worsens the GIDL effect in contemporary devices.
To overcome the GIDL effect, devices are being configured to include dummy word lines inserted between the ground select line GSL and the first word line W0, and dummy memory cells inserted between the corresponding ground select transistors and the first memory cell transistors driven by the first word line W0, increasing the distance between them. However, this approach consumes valuable chip area, which is at a premium in highly integrated devices.